1. Field of the Invention
The embodiments discussed herein relate to a semiconductor device.
2. Description of the Related Art
Use of a bootstrap circuit to supply voltage to a high-side (high-potential) circuit portion of a high voltage integrated circuit (HVIC) is generally known. A capacitor in the bootstrap circuit operates such that constant voltage may be supplied to the high-side circuit portion while repeating discharge and charge. However, voltage abnormality may occur in the bootstrap circuit whereby sufficient voltage may not be supplied from the capacitor in the bootstrap circuit to the high-side circuit portion. As a semiconductor circuit device to avoid this problem, a device has been proposed that monitors the voltage applied to both ends of a bootstrap capacitor to control ON/OFF at the output stage at the time of voltage abnormality of the bootstrap capacitor (see, e.g., Japanese Laid-Open Patent Publication Nos. H11-027950 and 2013-085419).
A configuration of a conventional semiconductor circuit device including a bootstrap circuit will be described. FIGS. 7 and 9 are circuit diagrams of circuit configurations of conventional semiconductor circuit devices. FIG. 8 is a circuit diagram of detailed configurations of circuit blocks of FIG. 7. In FIGS. 7 to 9, identical constituent elements are denoted by the same reference numerals. FIGS. 7 and 8 are FIGS. 1 and 2 of Japanese Laid-Open Patent Publication No. H11-027950. FIG. 9 is FIG. 1 of Japanese Laid-Open Patent Publication No. 2013-085419. The semiconductor circuit device depicted in FIG. 7 is a load drive circuit supplying electric power to a load 111 connected to a connection point of two transistors 101, 102 making up one phase of a half-bridge circuit serving as an output stage. This semiconductor circuit device includes first and second drive circuits 103, 104, a bootstrap diode 105, a bootstrap capacitor 106, a voltage detection circuit 109, first and second level shift circuits 107, 108, and a refresh operation circuit 110.
The first drive circuit 103 controls the gate drive of the high-potential transistor (hereinafter referred to as the upper arm transistor) 101 based on a control signal input from a first input terminal 121. The second drive circuit 104 controls the gate drive of the low-potential transistor (hereinafter referred to as the lower arm transistor) 102 based on a control signal input from a second input terminal 122. The source of the upper arm transistor 101 is connected to a bootstrap circuit made up of the bootstrap diode 105 and the bootstrap capacitor 106. The bootstrap circuit keeps a bootstrap voltage VBS of an upper arm constant. Thus, the bootstrap capacitor 106 is charged by a control power source voltage VCN applied via the bootstrap diode 105.
The first level shift circuit 107 shifts the level of the control signal input from the first input terminal 121 and supplies the control signal to the first drive circuit 103. The second level shift circuit 108 shifts the level of a signal based on an output signal of the voltage detection circuit 109 and supplies the signal to the refresh operation circuit 110. The refresh operation circuit 110 determines whether a refresh operation is to be performed, based on a detection signal of the voltage detection circuit 109. The voltage detection circuit 109 uses voltage-dividing resistors R1, R2 (see FIG. 8) connected in parallel with the bootstrap capacitor 106 to monitor the voltage applied to both ends of the bootstrap capacitor 106 (hereinafter referred to as a bootstrap voltage VBS).
Based on the signal from the second level shift circuit 108, the refresh operation circuit 110 supplies a signal controlling the lower arm transistor 102 to the second drive circuit 104. If the voltage detection circuit 109 detects that the bootstrap voltage VBS becomes equal to or lower than a predetermined voltage (at the time of occurrence of voltage abnormality), the refresh operation circuit 110 is supplied with the detection signal of the voltage detection circuit 109, with the level being shifted by the level shift circuit 108. In this case, for example, the refresh operation circuit 110 outputs a control signal making an ON period of the lower arm transistor 102 longer to prolong the charge period of the bootstrap capacitor 106.
As is the case with the semiconductor circuit device depicted in FIG. 7, the semiconductor circuit device depicted in FIG. 9 includes the two transistors 101, 102, the first and second drive circuits 103, 104, the bootstrap diode 105, the bootstrap capacitor 106, and the voltage detection circuit 109. The semiconductor circuit device depicted in FIG. 9 further includes a suspension period control circuit 112. In the semiconductor circuit device depicted in FIG. 9, when the bootstrap voltage VBS is detected to become lower than a predetermined voltage (at the time of occurrence of voltage abnormality), the voltage detection circuit 109 suspends output of a gate signal to the upper arm transistor 101. In this case, the suspension period control circuit 112 detects the suspension of the output of the gate signal to the upper arm transistor 101 and controls the voltage detection circuit 109 so as not to prolong the period of suspended output of the gate signal more than necessary.
With progressive advancements in the functionality of HVICs, a recently proposed device includes a function of detecting an output potential VS of a half-bridge circuit serving as an output stage so as to correct deviation of output voltage. The output potential VS is detected by using a resistive element built-in between the output potential VS and a ground potential GND of the HVIC, for example.